This is collection of Synchronization Components can be used to synchronize across different clock domains for control and Data Transfer.
This library carry following components -
For Control/ 1bit data
1. Single bit Control Transfer Sync
2. Multi Bit Control Transfer Sync.
3. Single Bit Pulse Transfer Sync
4. Multi Bit Pulse Transfer Sync
5. Multi-Bit Data Sync
6. Synchronous Clock and Reset Generator.
7. Reset Sequencer.
This is collection of Synchronization Components can be used to synchronize across different clock domains for control and Data Transfer
Overview
Key Features
- Features -
- These Component Fixes -
- 1. Glitch Sampling.
- 2. Re convergence
- 3. Reset Domain Crossing.
- Following are the options -
- 1. Clock Ratio Selection.
- 2. Data/ Control Signal Width Selection.
Benefits
- 1. Using Stable and Tested Standard block decrease time to clean up CDC issues in later stages.
- 2. Standard Synchronizer Flops and Signal names make it much easy to identify and extract list of synchronizers. One need not to depend on tools and iterations across them.
- 3. Makes IP More stable to operate.
Applications
- Internal IP Component Block
- can be used inside any IP/SOC.
Deliverables
- Standard Deliverables list -
- 1. Source Code in verilog.
- 2. Test Bench.
- 3. Simulation Scripts.
- 4. Synthesys scripts.
- 5. Documentation
- 6. User Guide.
Technical Specifications
Maturity
Final, Stable, tested
Availability
Avaliable
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