The SSL1 core implements SSL and/or TLS frameworks with a configurable variety of cipher suites.
SSL1-AXI has a “lookaside” interface to the rest of system through two AXI interfaces:
•AXI3/AXI4 slave for control
•AXI3/AXI4 master for data transfer
The data stream through the control interface contains processing commands. Each command consists a pointer to the descriptor in the system memory. Descriptor contains source, destination, encryption context, processing length, and status.
The encryption context (keys, encryption state, etc.) as well as the packets are stored in the system memory attached to the AXI bus and are read and written via the master interface.
The design is fully synchronous and is available in Verilog.
SSL/TLS Processor IP Core with an AXI Bus Interface
Overview
Key Features
- Throughput of 6-8 bits per clock (600-800 Mbps at 100 MHz)
- Supports both encryption and decryption
- Optional public-key RSA and ECC engines
- Done signal for interrupting the CPU
- Test bench provided
Block Diagram
Applications
- Embedded SSL/TLS applications
Technical Specifications
Related IPs
- Enhanced SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus. Supports eSPI Master & Slave and SPI Master & Slave functions
- I2C Controller IP- Master / Slave, Parameterized FIFO, AXI Bus
- I2C Controller IP – Master, Parameterized FIFO, AXI Bus
- SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- SPI Controller IP- Master-only, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU