SCR5 is an efficient, silicon-proven, entry-level Linux-capable 32/64-bit RISC-V processor core.
The SCR5 core fully supports RISC-V standard "I" Integer, "M" Integer Multiplication and Division, "A" Atomic, "C" 16-bit Compressed, "F" Single-Precision Floating-Point, "D" Double-Precision Floating-Point, “B” Bit Manipulation, and “K” Scalar Cryptography extensions. SCR5 includes an in-order 9-stage pipeline, a floating-point unit, a branch prediction unit for efficient code execution, PLIC, ACLINT, IPIC/CLIC units for efficient interrupt processing, and industry-standard AXI4, JTAG, and cJTAG interfaces increasing flexibility and compatibility.
The SCR5 memory subsystem includes a TCM unit, L1 and L2 caches, an MMU unit and supports the execution of real-time and Linux operating systems. The processor core can operate in heterogenous multicore (up to 4 cores in a cluster) environments, offering hardware-level support for memory coherency and simplified external accelerators' integration.
SCR5 Key Features
| Core | |
|---|---|
| ISA | RV32/RV64(IMC[AFDBK]) Atomic instructions [A], Single-Precision Floating-Point Instructions [F], Double-Precision Floating-Point Instructions [D], Bit Manipulation [B], Scalar Cryptography Instructions [K] — optional |
| Pipeline | 7-9 stages |
| Floating-Point Unit (FPU) | Single/Double-precision, IEEE 754-2008 standard |
| Multicore Support (SMP) | Up to 4 cores with cache coherency |
| Branch Prediction Unit (BPU) | Static/Dynamic |
| Memory Subsystem | |
| Tightly-Coupled Memory (TCM) | Up to 256KB, error protection — parity/ECC |
| L1 Cache | Up to 64KB + 64KB, error protection — parity/ECC |
| L2 Cache | From 128KB to 512KB, error protection — ECC |
| Memory Management Unit (MMU) | Up to 64 TLB instruction entries, up to 64 TLB data entries |
| Memory Protection Unit (MPU) | Configurable, up to 32-region MPU |
| Security | |
| CFI (Control Flow Integrity) | Shadow stack and landing pads support |
| Interrupt Subsystem | |
| IPIC | Up to 32 interrupt lines |
| CLIC | Up to 4096 interrupt lines, up to 256 priority levels |
| PLIC | Up to 1023 interrupt lines, up to 256 priority levels |
| ACLINT | Up to 4096 interrupt lines |
| Debug Subsystem | |
| Interface | JTAG/cJTAG-compliant interface |
| Breakpoints | Up to 8 hardware breakpoints, unlimited software breakpoints support |
| Interfaces | |
| AXI | Master AXI4 AMBA standard interface |
| AHB | Master AHB AMBA standard interface |
| External Ports | TCM AXI slave port, L2 cache coherency port |
| Timers and Counters | |
| Performance Monitoring | Up to 32 performance counters |
| Embedded 64-bit RTC Timer | Machine-mode and Supervisor-mode timer interrupt support (sstc) |
Development Tools
Syntacore Development Toolkit (SCR5 Optimized)
The SC-DT package is a ready-to-use software development kit containing pre-built and pre-configured tools that simplify software development for the SCR5 core. With SC-DT, you can take advantage of the pre-built tools and configurations to reduce the time and effort required to get up and running with SCR5. SC-DT supports Windows, Linux, and RISC-V Linux operating systems and includes:
- Eclipse IDE and Visual Studio Code plugin
- Compilers (GCC, clang/LLVM with microarchitecture optimizations and optimized libraries for Linux)
- Debuggers (GDB with gdbserver, OCD)
- Simulator (QEMU)
- FreeRTOS and Linux operating systems
- OpenSBI and U-boot bootloaders
- Native Toolkit (designed to run on the RISC-V SCR Linux host)
- HAL and BSP
- Application examples
- Benchmarks
- Documentation
Syntacore also supports and maintains system software such as Linux, Zephyr, OpenJDK, and U-boot that are not part of the SC-DT package and are downloadable separately.
