SMTPE-292 Scrambler & Descrambler / Framer

Overview

The SMPTE292 core set, coupled with the AMCC S8401/S8501 serializer/deserializer chipset is fully compliant to the SMPTE 292M specification for Bit Serial Interfaces for High Definition Television Systems. The core set includes separate Xilinx Virtex/Spartan-II cores for transmitter coding (scrambling and NRZI) and receiver decoding (NRZ, descrambling, sync detect and word framing).

The CORE set is supplied as two cores, one for transmit and one for receive. The block diagrams are shown in Figure 1 in a system context. The cores may be purchased separately or as a set.

Key Features

Fully compatible with SMPTE specification for 292M Bit-Serial Digital Interface for High Definition Television Systems
Designed for use with AMCC S8401/S8501 serializer and deserializer chipset
Separate Macro blocks for transmit scrambler and receiver descrambler/framer
Fully synchronous operation
>75 MHz performance in all compatible devices
Transmit macro accepts 20 bit parallel data (10 bit EY and 10 bit ECb ECr), then codes it using the scramble polynomial (X9 + X4 + 1) and NRZI (x+1) encoding. Outputs 20 bits parallel to AMCC S8401serializer on each cycle of transmit word clock.
Receive macro accepts 20 bit de-serialized data from AMCC S8501 deserializer, reverses the NRZI coding and descrambles the data.Framing logic aligns the bits with the 20 bit parallel output (aligns 10 bit EY and 10 bit ECb ECr)
Both Macros are relatively placed to ensure a successful route and timing

Block Diagram

Applications

The SMPTE 292 Scrambler and Descrambler/Framing Cores are used with the AMCC S8401/S8501 High Definition Serial Interface (HD-SCI) chipset. The chipset and these cores form the basic SMPTE 292M interface for HDTV applications.

Technical Specifications

Availability

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