Best-in-class Arm® AMBA® LTI Verification IP (VIP) for your IP, SoC, and system-level design testing.
Cadence provides a mature and comprehensive Verification IP (VIP) for the LTI specification, which is part of the Arm® AMBA® family of protocols. Incorporating the latest protocol updates, the Cadence Verification IP for LTI provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Cadence provides Interconnect Validator connection for interconnect verification that verifies the correctness and completeness of data as it passes through the SoC. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for LTI helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
Supported specification: AMBA® LTI Protocol Specification (Includes both Issue A and Issue B spec)
