IP Catalog > Peripheral IP > AMBA AHB / APB/ AXI IP > AMBA AHB / APB IP > Simulation VIP for AMBA AHB

Simulation VIP for AMBA AHB

Overview

Cadence provides a mature and comprehensive Verification IP (VIP) for the AHB specification which is part of the Arm® AMBA® family of protocols. Incorporating the latest protocol updates, the Cadence® Verification IP for AHB provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Cadence provides an integrated solution for interconnect verification that verifies the correctness and completeness of data as it passes through the system and performance analysis that provides automated generation of testbenches. It also provides a ready-to-use Test Suite that is composed of semi-directed tests with a limited level of randomness. The VIP for AMBA AHB is it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification and is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

Supported specification: AMBA AHB v2.0, AMBA 3 AHB-Lite Protocol v1.0, AMBA 5 AHB5 update, and Armv6 AMBA Extensions

Key Features

  • Multiple Agents
    • Can support any number of agents
  • Data and Address Widths
    • Supports all legal data and address widths
  • Automatic subordinate Responses
    • Configurable option to use automatic subordinate responses
  • Delay Control
    • Support to set the delay between the items on the channels
  • Manager Signals Control
    • Support for control over the values of burst signals in the read and write address channel and over the values of transfer signals in the write data channel
  • Memory Monitoring
    • Memory can be set using backdoor access
  • Subordinate Response Control
    • Support for control over the signals in the read data channel
  • Subordinate Memory Emulation
    • Data consistency check for subordinates using memories
  • Transaction Types
    • Supports monitoring and driving of all read and write transactions
  • Hunalign and Hstrb
    • Support for Hunalign and Hstrb signals. To handle unaligned accesses and mixed-endian accesses, enables the use of byte lane strobes to indicate which byte lanes are active in a transfer
  • Subordinate Responses
    • Supports all Subordinate Responses - OKAY, ERROR, SPLIT, RETRY, and XFAIL (XFAIL is relevant only for ARMv6 AMBA Extensions)
  • Lite Cortex-M3
    • Support retraction as defined in the Arm Cortex® -M3 spec
  • AHB-Lite
    • Support for Secure Transfers, Exclusive Transfers, Extended Memory Types, Multiple Subordinate Select, User Signaling, and Single-Copy Atomicity features introduced in AMBA5 AHB
  • Exclusive Accesses
    • Support for exclusive access (Armv6 AMBA extension)
  • Level 2 Cache
    • Level 2 Cache Support (Armv6 AMBA extension)

    Block Diagram

    Simulation VIP for AMBA AHB Block Diagram

    Technical Specifications

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