Cadence provides a mature and comprehensive Verification IP (VIP) for the LPI specification which is part of the Arm® AMBA® family of protocols. Incorporating the latest protocol updates, the Cadence® Verification IP for LPI provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Cadence provides Interconnect Validator connection for interconnect verification that verifies the correctness and completeness of data as it passes through the SoC. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for LPI helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
Supported specification: Arm® Q-Channel and P-Channel Interfaces of Low Power Interface Specification
