Serial ATAIP- Host Controller
Overview
The Mentor Graphics?Serial ATA(SATA) Host Controller provides an efficient and easy-to-use interface to SATA devices. The core implements transfer speeds of either 150 MB/s or 300 MB/s and emulates programmable I/O, multi-word direct memory access (DMA), and Ultra ATA modes of operation. The core interface to the SoC includes a DMA controller to optimize data transfers to and from the IDE devices and provides PIO access via shadow registers. For ease of integration, the core includes a register set that it compatible with the Intel chip set.
Key Features
- Compliant with the Serial ATA specification version 2.6
- Supports 1.5 Gb/s (150 MB/s) or 3 Gb/s (300 MB/s) speeds
- Supports Native Command Queuing (NCQ)
- Support for Spread Spectrum Clocking (SSC)
- Descriptor-based, scatter-gather DMAengine
- Intel register set compatible
- Synchronous DMAinterface for data transfers
- Supports 10-, 20-, or 40-bit SATA standard PHYinterface
- Asynchronous Notification
- Supports either CoreFrame or AMBA AHB 2.0 bus interface
Deliverables
- Verilog RTLsource code
- Example synthesis scripts
- Verilog functional verification environment with tasked-based verification and PHmodel
- Detailed specifications including user guide, product specification, verification guide, and programmers guide
Technical Specifications
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