SDRAM Memory Model

Overview

SDRAM Memory Model provides an smart way to verify the SDRAM component of a SOC or a ASIC. The SmartDV's SDRAM memory model is fully compliant with standard SDRAM Specification and provides the following features. Better than Denali Memory Models.

SDRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SDRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports SDRAM memory devices from all leading vendors.
Supports 100% of SDRAM protocol standard 512Mb_sdr & HY57V56820FT-H
Supports Internal banks for hiding row access/precharge
Supports Programmable burst lengths: 1, 2, 4, 8, or full page
Supports Auto precharge, includes concurrent auto precharge and auto refresh modes
Supports Self refresh mode
Supports Auto refresh
Supports programmable clock frequency of operation
Supports all types of timing and protocol violation detection
Supports for All Mode registers programming
Supports for Speed Grade

Supports all the SDRAM commands as per the 512Mb_sdr & HY57V56820FT-H
Checks for following

Check-points include power on, Initialization and power off rules,
State based rules, Active Command rules,
Read/Write Commands rules etc.
All timing violations.

Bus-accurate timing for min, max and typical values
Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
Constantly monitors SDRAM behavior during simulation
Protocol checker fully compliant with SDRAM Specification 512Mb_sdr & HY57V56820FT-H
Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
Built in functional coverage analysis
Supports Callbacks, so that user can access the data observed by monitor.

Benefits

Faster test bench development and more complete verification of SDRAM designs.
Simplifies results analysis.
Integrates easily into OpenVera, System Verilog, System C, Verilog
Runs in every major simulation environment
Written in 100% SytemVerilog and VMM. So runs faster and easy to use with VMM test benches.

Block Diagram

Deliverables

Complete regression suite containing all the SDRAM testcases.
Complete UVM/OVM sequence library for SDRAM controller.
Examples showing how to connect and usage of Model.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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