CRISP is a CPU Core built by integrating our PNU with 64-bit RISC-V Processor. RISC-V is a royalty free open-ISA. CRISP makes use of Bluespec Inc’s Flute core (open-source RISC-V) core. CRISP was extensively verified using Bluespec’s RV-factory.
CRISP as world’s first posit-capable RISC-V CPU was demonstrated at RISC-V Workshop in Zurich in June’19. CRISP –core in virtual form booting Linux and running C/C++ applications natively using posits was demonstrated using FPGAs.
CRISP can be used as the fundamental computing core for building posit-enabled System-on-Chip (SoCs) for many applications.
RISC-V Processor With Posits
Overview
Deliverables
- Verilog RTL of CRISP core for Posit <32,2> and <64,3> configurations
- Design verified using FPGAs, runs Linux and C/C++ applications in native posit world
- Enhanced Cross-compiler to generate binaries for native-posit computations
- No need for any source-level changes for any applications
- Posit-enabled Math Libraries