RISC-V Processor IP

Welcome to the ultimate RISC-V Processor IP hub! Explore our vast directory of RISC-V Processor IP.

RISC-V is an open-source instruction set architecture used to develop custom processors for a variety of applications, from embedded designs to supercomputers.

Unlike proprietary processor architectures, RISC-V is an open-source instruction set architecture (ISA) used for the development of custom processors targeting a variety of end applications.

All offers in RISC-V Processor IP

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Compare 128 RISC-V Processor IP from 28 vendors (1 - 10)

32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32/64 Bit RISC-V core
- 5-stage pipeline
- In-order, Single issue
- Multicore Capable (up to 8 cores)
Dual-issue Linux-capable RISC-V core
- 64-bit RISC-V core
- RVA22 profile
- Linux capable
64-bit RISC-V Application Processor Core
- 64-bit RISC-V core
- Linux capable
- In-order 7-stage pipeline
32 Bit - Embedded RISC-V Processor Core
- 32 bit,
- 3-stage pipeline,
- 32 registers
32 bit - Compact RISC-V Processor Core
- 32-bit RISC-V core
- RV32EMC instruction set
- 16 general purpose registers
Processor Development Toolset
- A unified development model describing the processor in a single CodAL description
- High performance processor synthesis
- Complete UVM verification environment
- Advanced profiling and analysis
RISC-V high performance CPU
- Aggressive eight-wide deep out-of-order pipeline
- Unique 512KB IL2(I-cache) with DL1/DL2 (512KB) split vs unified 1MB L2
32 Bit - Embedded RISC-V Processor Core
- Best-in-class performance for small-area and low-power applications
- Highly configurable and easy and quick to customize and verify
- Process compliant with ISO 26262 and ISO 21434
Ultra-Low-Power Deeply Embedded RISC-V Processor
- Small silicon footprint for lower leakage and dynamic CPU power
- Advanced power management
- Single-issue, in-order, 2-stage pipeline
32b/64b RISC-V 2-stage, scalar, in-order, Embedded Processor. RTOS and multi-core capable. Maps upto ARM M-4F. Optimal PPA.
- 32-bit RISC-V core
- 2-stage pipeline
- Available in many versions: RV32I[M][C][F][B][P][U]
- 32/16 general purpose registers