NetTimeLogic’s DCFSlave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to a DCF signal encoded as PWM. The encoding scheme is the one of the DCF77 sender near Frankfurt, Germany. The whole encoding, algorithms and calculations are implemented in the core, no CPU is required. This allows running DCF synchronization completely independent and standalone from the user application. The core can be configured either by signals or by an AXI4Light-Slave Register interface.
All calculations and corrections are implemented completely in HW.
Radio Clock (DCF77) Slave core
Overview
Key Features
- DCF Slave Clock
- Supports DCF-77 format
- Optional Signal Filter
- DCF decoding and time format conversion
- DCF supervision
- Input delay compensation
- Air propagation delay compensation
- No Leap second handling and daylight saving time
- Additional seconds correction to convert between UTC and TAI time (or any other time base)
- Synchronization accuracy: +/- 10 ms
- AXI4 Light register set or static configuration
- Timestamp resolution with 50 MHz system clock: 20ns
- Hardware PI Servo
Benefits
- Coprocessor handling Radio Clock (DCF77) synchronization standalone in the core.
- Simple interface
Block Diagram
Applications
- Distributed data acquisition
- Ethernet based automation networks
- Automation
- Robotic
- Automotive
- Test and measurement
Deliverables
- Source Code (not encrypted, not obfuscated)
- Reference Designs
- Testbench with Stimulifiles
- Configuration Tool
- Documentation
Technical Specifications
Availability
Now
Related IPs
- Radio Clock (DCF77) Master core
- IEEE 1588 V2 CPU-less Slave Clock
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- I3C Controller IP – I3C / I2C Slave, SCL Clock only, Configure User Registers, no CPU Host Required
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