The DB-I3C-S-SCL-CLK-REG is an I3C Slave Controller IP Core focused on low power, low noise, low VLSI footprint ASIC / ASSP designs requiring the configuration & control of registers with no free running clock. The DB-I3C-S-SCL-CLK-REG processes the I3C protocol & physical layers, and receives & transmits bytes with respect to the I3C payload to / from User Registers within an ASIC / ASSP / FPGA device. The DB-I3C-S-SCL-CLK-REG Controller implements the Slave-Transmit and Slave-Receive protocol according to the MIPI I3C-Basic-Spec-ver1_0 specification.
The DB-I3C-S-SCL-CLK-REG builds on Digital Blocks DB-I2C-S-SCL-CLK Controller and supports I2C Master Slave-Transmit and Slave-Receive protocol according to the Philips I2C-Bus Specification, Version 2.1 as well as the updated NXP Rev .5 October 9, 2012 Specification.
The gigure below depicts the system view of the DB-I3C-S-SCL-CLK-REG Controller IP Core embedded within an ASIC, ASSP or FPGA device. The DB-I3C-S-SCL-CLK-REG Controller receives and transmits data with respect to an external I3C or I2C Master Controller. The DB-I3C-S-SCL-CLK-REG internally interfaces to User Registers / Memory.