PVCI (Peripheral VCI) Verification IP

Overview

PVCI (Peripheral VCI) Verification IP provides an smart way to verify the PVCI (Peripheral VCI) component of a SOC or a ASIC. The SmartDV's PVCI (Peripheral VCI) Verification IP is fully compliant with standard PVCI (Peripheral VCI) Specification and provides the following features.

PVCI (Peripheral VCI) Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

PVCI (Peripheral VCI) Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Compliant to PVCI (Peripheral VCI) Protocol version 2.0
Supports PVCI Initiator, PVCI Target, PVCI Monitor and PVCI Checker.
Supports all PVCI data and address widths.
Supports 8-bit, 16-bit and 32-bit devices.
Supports 8-bit, 16-bit and 32-bit transfers.
Simple packet and burst transfer support.
Optional Free-BE mode support.
Target supports fine grain control of response per address or per transfer.
Programmable wait state and timeout insertion.
Ability to inject errors during transfers.
Configurable PVCI interface size for read and write transfers.
Supports constrained randomization of protocol attributes.
Flexibility to send completely configured data.
Supports FIFO memory.
Rich set of configuration parameters to control PVCI (Peripheral VCI) functionality.
On-the-fly protocol and data checking.
Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
Built in coverage analysis.
Callbacks in Initiator, Target and monitor for various events.
Status counters for various events on bus.
PVCI (Peripheral VCI) Verification IP comes with complete testsuite to test every feature of PVCI (Peripheral VCI) specification.

Benefits

Faster testbench development and more complete verification of PVCI (Peripheral VCI) designs.
Easy to use command interface simplifies testbench control and configuration of Initiator and Target.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the PVCI (Peripheral VCI) testcases.
Examples showing how to connect various components, and usage of BFM and Monitor.
Detailed documentation of all classes, tasks and functions used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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