The programmable CMOS frequency divider consists of two independent circuits. The first one a set of 8 serially connected dividers with the varied dividing ratio 2/3. This structure is especially effective for wide range of dividing ratio since the number of triggers to accomplish the specified ratio is minimized. The second divider is based on the prescaler with the varied dividing ratio 4/5 and the two programmable binary-decimal counters.
The dividing ratio is 16…4095. Input frequency is 1000...1900 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
Programmable CMOS HF divider (16…4095 dividing ratio)
Overview
Key Features
- iHP SGB25V
- Wide range of dividing ratio (16…4095)
- High operating frequency
- Low current consumption
- Compact structure
- Portable to other technologies (upon request)
Applications
- PLL frequency synthesizer
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
iHP SiGe BiCMOS 0.25 um
Maturity
Pre-silicon verification
Related IPs
- Programmable 9-bit CMOS frequency divider (2…511 dividing ratio)
- Programmable CMOS frequency divider (32...16383 dividing ratio)
- Programmable 9-bit CMOS low-frequency divider (5...511 dividing ratio)
- Programmable CMOS frequency divider (56..16383 dividing ratio)
- Programmable frequency divider (56 to 16383 dividing ratio)
- 4-bit programmable ECL LF divider (1…15 dividing ratio )