Power On Reset (POR)

Key Features

The Power on Reset circuit has three configuration and their specifications are listed as below:
- Mode0 1.8 and Mode1 3.3 V supply mode
- MODE 0 Rise and Fall Delay on a slope of 1V/1µs 2.184 and 3.194 µs respectively.
- MODE 0 Rise and Fall Delay on a slope of 1V/100ns 1.284 and 3.144 µs respectively.
- MODE 1 Rise and Fall Delay on a slope of 1V/1us 5.202 and 8.483 µs respectively.
- MODE 1 Rise and Fall Delay on a slope of 1V/100ns 5.068 and 8.279 µs respectively.
- Quiescent Current 5.176 µA
- Area 200 um X 200 um
- Technology Node: GF 40nm 1P7M
Note: The POR can be configured for both the modes and just for one of the modes Mode 0 and Mode 1 which can work on different supply voltages VDDA and VBAT as shown in Figure 1

Start-Up Reset:
- During power-up, the POR triggers the initial system reset. This ensures that the processor or other components start execution from a well-defined state.
Voltage Monitoring:
- The POR continuously monitors the supply voltage. If supply voltage falls below a certain threshold due to noise, glitches, or power fluctuations, the POR activates a reset pulse. This prevents the IC from operating in an undefined or unreliable state.
Failure Detection:
- Unexpected voltage drops (e.g., due to a faulty power supply) can lead to system instability. The POR detects such failures and initiates a reset to prevent erratic behavior.
Safe Operation:
- By enforcing a stable start-up sequence, the POR contributes to overall system reliability.

Short description

Vendor

Vendor Name

Foundry, Node

40nm GF

Availability

Immediate