PLL IP, Input: 10MHz - 200MHz, Outout: 50MHz - 1000MHz, UMC 90nm SP process
Overview
This Phase-Locked Loop (PLL) based clock multiplier.
Technical Specifications
Short description
PLL IP, Input: 10MHz - 200MHz, Outout: 50MHz - 1000MHz, UMC 90nm SP process
Vendor
Vendor Name
Foundry, Node
UMC 90nm SP
UMC
Pre-Silicon:
90nm
SP
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