PLL (Frequency Synthesizer) IP, Input: 10MHz - 50MHz, Output: 10MHz - 200MHz, UMC 40nm LP process
Overview
Input 10-50MHz, output 10-200MHz, frequency synthesizable PLL, UMC 40nm LP/RVT Logic process(Note:same schematic with FXPLL010HH0L, but Poly Density Errors are waived in layout for 40% area reduced.).
Technical Specifications
Foundry, Node
UMC 40nm LP
UMC
Pre-Silicon:
40nm
LP
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