PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 300MHz - 600MHz, UMC 65nm LL process
Overview
Input 20M-200MHz, output 300M-600MHz, frequency synthesizable PLL, UMC 65nm LL Logic/RVT Low-K process.
Technical Specifications
Foundry, Node
UMC 65nm LL
UMC
Pre-Silicon:
65nm
LL
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