PLL (Frequency Synthesizer) IP, Input: 10MHz-200MHz, Output: 25MHz - 400MHz, UMC 0.11um SP/FSG process
Overview
Input 10MHz~200MHz, output 25MHz~400MHz, frequency synthesizable PLL, UMC 0.11um SP/FSG Logic process.
Technical Specifications
Foundry, Node
UMC 110nm SP/FSG
UMC
Pre-Silicon:
110nm
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