IP Catalog > Interface IP > Interconnect IP > PCI IP > PCI Express IP > PCI Express Controller IP > PCIE Gen6 digital controller (Root Complex)

PCIE Gen6 digital controller (Root Complex)

Overview

PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE specification Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications.

Key Features

  • Compliant wiPCIE Gen 6 Spec.
  • Compliant wiPipe 5.X Spec.
  • PrimeSOC’s PCIE Gen 6.O Core supports Flit and non – Flit Mode.
  • Supports X16, X8, X4, X2, X1 Lane Configuration.
  • AXI MM and Streaming supported.
  • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6 modes.
  • Data rate support of 2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s, 32 GT/s, 64 GT/s.
  • PAM support when operating at 64GT/s
  • 8b/10b,128b/130b,1b/1b encoding , decoding support.
  • Supports serdes and non – serdes architecture.
  • Optional DMA support as plugin module.
  • Support for alternate negotiation protocol.
  • Lane polarity thru register control.
  • Lane deskew supported.
  • Support for L1 states.
  • L0P Supported.
  • SKP OS add/removal.
  • SRIS mode supported.
  • No equalization support thru configuration.
  • Deemphasis negotiation support at 5GT/s.
  • EI inferences in all modes.
  • PTM, OBFF, MSI, MSIX, Power management and all message format supports.

Deliverables

  • Verilog soft IP
  • Sample testbench

Technical Specifications

Availability
Immediate
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