PCIe 6.1 Controller

Overview

Key Features

• Designed to the latest PCI Express 6.1 (64 GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s), and PIPE 6.x (8-, 16-, 32-, 64- and 128-bit) specifications
• Supports SerDes Architecture PIPE 10b/20b/40b/80b width
• Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
• Supports multiple virtual channels (VCs) in FLIT and non-FLIT modes
• Supports Endpoint, Root-Port, Dual-mode, Switch port configurations
• Supports x1 to x16 architectures at PCIe 6.1 to PCIe 1.0 speeds
• Supports Forward Error Correction (FEC) - Lightweight algorithm for low latency
• Supports L0p Low Power mode
• Supports AER, ECRC, ECC, MSI, MSI-X, Multifunction, crosslink, and other optional features
• Up to 4-bit parity protection for data path
• Supports Clock Gating and Power Gating
• RAS features include LTSSM timers override, ACK/NAK/Replay/UpdateFC timers override, unscrambled PIPE interface access, error injection on Rx and Tx paths, recovery detailed status and much more, allowing for safe and reliable deployment of IP in mission-critical SoCs

Benefits

• Optimized for high-bandwidth efficiency at data rates up to 64 GT/s
• Scalable data path
• Advanced PIPE modes and port bifurcation
• Supports multiple virtual channels (VCs) in FLIT and non-FLIT modes
• Supports Endpoint, Root-Port, Dual-mode, Switch port configurations
• Advanced RAS features
• Optional IDE security with AES-GCM encryption, decryption and authentication

Applications

• Data Center
• Edge
• AI/ML
• HPC

Deliverables

• IP files
• Verilog RTL source code
• Libraries for functional simulation
• Configuration assistant GUI
• Full Documentation
• Reference Designs
• Synthesizable Verilog RTL source code
• Simulation environment and test scripts
• Synthesis project & DC constraint files (ASIC)

Technical Specifications