DMA Controller

Key Features

• Multiple independent DMA channels
• Designed with synthesizable HDL for ASIC and PLD implementations in various system environments
• Each channel programmable to two types of DMA transfers: memory-to-memory and memory-to-I/O data transfer.
• Supports both hardware initiated transfer and software initiated transfers.
• Programmable burst and single data transfer.
• Internal arbitration logic for multiple DMA channels.
• Interrupt generation on transfer completion.
• Optional DMA chaining for multiple DMA sessions.
• Differentiating Features
  • Select number of DMA channels.
  • Program number of bits in the transfer control registers.
  • Chose a fix or rotating arbiter priority scheme.

Block Diagram

Technical Specifications