PCIe 6.0 PHY in Samsung (SF5A, SF4X, SF2)

Overview

The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interface card (NIC), backplane, and chip-to-chip interfaces. The PHY’s unique DSP algorithms optimize analog and digital equalization and the patent-pending diagnostics features enable near zero link downtime. The PHY minimizes package crosstalk, allows dense SoC integration for x16 links, and achieves ultra-low-latency with an optimized data path that is based on an ADC architecture. Support for multiple standards form factors including OCP 3.0, U.2, and U.3 enables server and storage applications.
The Synopsys PHY IP for PCIe 6.0 seamlessly interoperates with Synopsys Controller IP for PCIe 6.0 to provide a low-risk solution that designers can use to accelerate time-to-market and efficiently deliver differentiated products that require the 64GT/s PCIe 6.0 technology.

Key Features

Physical Coding Sublayer (PCS) block with PIPE interface
Supports PCIe 6.0, encoding, backchannel initialization
Supports PCIe Lane Margining at Receiver
Spread-spectrum clocking (SSC)
PCIe power management features, including L0p substate; power gating and power island
The multi-channel PHY macro with single clock and control core for higher density with support for both internal and external reference clock inputs
PIPE bifurcation as well as PHY macro aggregation for up to 16-lane configurations
Superior Rx jitter & cross talk tolerance reduces design constraints for a wider range of board layout designs
Automated Test Equipment (ATE) test vectors for complete at-speed production testing
Each PHY channel contains its own 7-, 9-, 11-, 13-, 15-, 23-, and 31-bit pseudo random bit sequencer (PRBS), or a user-defined custom 256-bit pattern for internal and external loopbacks
Each channel is fully controllable via the integrated logic core as well as the test access port (TAP)

Benefits

Supports the latest features of PCIe 6.0 specification
Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
Delivers more power efficiency across channels with unique DSP algorithms
Enables near zero link downtime with patent-pending diagnostic features
Minimizes package crosstalk with placement-aware architecture
Allows consistent performance across PVT variation with ADC/DSP-based architecture
Supports PCIe Lane Margining at Receiver
Supports L0p substate power state, power gating and power island
Embedded bit error rate tester (BERT), non-destructive internal eye monitor, and first bit error rate (FBER)
Built-in Self Test vectors, pseudo random bit sequencer (PRBS) generation and checker
Supports -40°C to 125°C junction temperatures
Supports flip-chip packaging

Applications

High-performance computing, storage area networks, networking switches, routers
Artificial Intelligence

Deliverables

Verilog models; Liberty timing views (.lib); LEF abstracts (.lef); CDL netlist (.cdl); GDSII; ATPG models IBIS-AMI models; Documentation

Technical Specifications

Foundry, Node

Samsung SF5A, SF4X, SF2 - SF5A, SF4X

Maturity

Available on request

Availability

Available

Samsung

Pre-Silicon: 4nm , 5nm

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