PCIe 2.0 PHY in UMC (40nm, 28nm)

Overview

The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for higher bandwidth. The PHY provides a cost-effective solution that is designed to meet the needs of today’s PCI Express (PCIe®) designs while being extremely low in power and area.
Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standard’s electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage, and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.
The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor
and test for signal integrity without the need for expensive test equipment. This provides on-ch°ip visibility into actual link and channel performance to quickly improve signal integrity, reducing both product development cycles and the need for costly field support.

Key Features

  • Physical coding sublayer (PCS) block with PIPE interface
  • Supports PCIe power management features, including L1 substate
  • Power gating for lowest standby power
  • Low active power using voltage mode TX with under drive supply options
  • The multi-channel PHY macro with single clock and control core for higher density
  • Supports both internal and external reference clock inputs
  • PIPE bifurcation as well as PHY macro aggregation for x8 and x16 PHY configurations
  • Multi-featured transmitter and receiver equalization
  • Each lane in a multi-channel PHY macro contains its own pseudo random bit sequencer (PRBS) for internal and external loopbacks, used to verify TX and RX circuitry
  • Each channel is fully controllable via the test access port (TAP) and core interface
  • The PHY IP is capable of mapping the signal eye, and outputs the signal statistics via JTAG interface

Benefits

  • Compliant with the PCI Express 2.1, 1.1, and PIPE specifications
  • x1, x2, x4, x8, x16 lane configurations with bifurcation
  • PCIe L1 substate power management
  • Supports power gating and power island
  • Embedded bit error rate tester (BERT) and internal eye monitor
  • ATE test vectors for complete, at-speed production testing
  • Pseudo random bit sequencer (PRBS) generation and checker
  • IEEE 1149.6 AC JTAG Boundry Scan
  • Beaconing, receiver detection and electrical idle features
  • Supports -40°C to 125°C junction temperatures

Applications

  • Desktops, laptops, workstations and servers
  • Embedded systems and set-top boxes
  • Network switches and routers
  • Enterprise computing and storage networks
  • Consumer portable devices
  • Graphics devices
  • Wireless devices

Deliverables

  • Verilog models
  • Liberty timing views (.lib)
  • LEF abstracts (.lef)
  • CDL netlist (.cdl)
  • GDSII
  • ATPG models
  • IBIS-AMI models
  • HSPICE models for TX and RX
  • Documentation

Technical Specifications

Foundry, Node
UMC 40nm, 28nm - LP, HPC+
Maturity
Available on request
Availability
Available
UMC
Pre-Silicon: 28nm , 40nm
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Semiconductor IP