PCI Bus Arbiter
Key Features
- Compliant with PCI bus specification 2.1 to 3.0
- Designed for ASIC and PLD implementations in various system environments.
- Supports two to eight bus masters.
- Run time selection between rotating priority or fix priority scheme.
- Bus parking.
- Single cycle request-to-grant turn around time.
- Quiet cycle during master switch.
- Master time-out.
Block Diagram
Technical Specifications
Short description
PCI Bus Arbiter
Vendor
Vendor Name
Foundry, Node
ASIC and FPGA
Availability
Now