64-bit PCI Bus Master/Target

Key Features

  • Fully supports PCI specification 2.1 and 2.2 protocol.
  • Supports both 64-bit and 32-bit bus systems.
  • Supports dual address cycle (DAC) 64-bit addressing.
  • Designed for ASIC and PLD implementations.
  • Fully static design with edge triggered flip-flops.
  • Combined bus master and target functions.
  • Efficient back-end interface for different types of bus slave and master devices.
  • Zero wait state burst data transfer.
  • Automatic transfer restart on target retry and disconnect.
  • High speed bus request and arbitration.
  • Parity generation and parity error detection.
  • Includes all PCI specific configuration registers.
  • Optimized for devices with slow output enable control.

Technical Specifications

Foundry, Node
ASIC and FPGA
Availability
Now
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Semiconductor IP