Vendor: Eureka Technology, Inc. Category: PCI

32-bit PCI Bus Master/Target

32-bit PCI Bus Master/Target

Key features

  • Compliant with PCI specification 2.2/2.3/3.0 protocol.
  • Designed for ASIC and FPGA implementations in various system environments.
  • Combines bus master and bus target functions in one core.
  • Supports burst transfer to maximize memory bandwidth.
  • Zero wait state PCI data transfer. Up to 133Mbyte/sec at 33Mhz and 266Mbyte/sec at 66Mhz.
  • Supports target retry, disconnect and target abort.
  • Automatic transfer restart on target retry and disconnect.
  • Concurrent bus master and target function.
  • Write buffer for target write data posting to increase PCI bus performance.
  • Responds to standard PCI configuration access.
  • Supports all PCI specific configuration registers.
  • User controlled base address register sizing and mapping.
  • Retry counter to limit bus access to non-responsive target device.
  • PCI status directly available to user logic for interrupt generation.
  • Differentiating Features
    • Asynchronous user interface
    • Power management.
    • DMA controller.
    • Direct interface to AMBA AHB, Mips or Power PC.
    • Dual address cycle.
    • Hot swap for compact PCI.
    • Host bridge function.

Block Diagram

EC220 block diagram

Specifications

Identity

Part Number
EC220
Vendor
Eureka Technology, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about PCI IP core

PCI Express Security and TEE Integration, Part 1 - Establishing Trust

Protecting processor memory alone is no longer sufficient. The entire I/O path must become part of the trusted computing architecture. To address this challenge, PCI-SIG® has developed a suite of complementary security technologies, including Data Object Exchange (DOE), Component Measurement and Authentication (CMA), Integrity and Data Encryption (IDE), and the TEE Device Interface Security Protocol (TDISP).

Frequently asked questions about PCI IP cores

What is 32-bit PCI Bus Master/Target?

32-bit PCI Bus Master/Target is a PCI IP core from Eureka Technology, Inc. listed on Semi IP Hub.

How should engineers evaluate this PCI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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