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OpenCAPI Verification IP

Overview

The SmartDV's OpenCAPI Verification IP is fully compliant with OpenCAPI TL V3.0, V3.1 and V4.0, OpenCAPI DL V1.0 and V1.5 Specifications and verifies OpenCAPI interfaces. It includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create the widest range of scenarios to verify the DUT effectively.

OpenCAPI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

OpenCAPI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Compliant with OpenCAPI Transport layer Specification versions 3.0, 3.1 and 4.0.
  • Compliant with OpenCAPI Data-link layer Specification versions 1.0 and 1.5.
  • Compliant with CFG Specifications v1.0 and v1.3.
  • Complete OpenCAPI Tx/Rx functionality.
  • Supports AFU interface functionality.
  • Supports the following Data-rates/speed.
    • 19.2 Gbps
    • 20.0 Gbps
    • 21.33 Gbps
    • 25.78125 Gbps
    • 25.6 Gbps
    • 31.875 Gbps
  • Supports Serial Interface and the SerDes width of 8, 10, 16, 20, 32, 64 bit.
  • Supports PHY Training and PHY Initialization.
  • Supports DL training sets.
  • Supports following lane reversal.
    • X8 or X4 Degraded Lane reversal
    • X4 (when X4 is running on 8 lanes)
  • Supports following lane degraded modes.
    • Odd lanes trained
    • Even lanes trained
    • Inside lanes trained
    • Outside lanes trained
    • Lane 1 trained
    • Lane 0 trained
  • Supports deskew markers.
  • Supports lane width detection and degraded mode flit transmission order.
  • Supports endpoint link speed discovery.
  • Supports Virtual channel (VC) and Data credit pool (DCP) specification.
  • Supports all DL and DLx packets.
  • Supports all TL and TLx packets.
  • Supports OpenCAPI memory interface.
  • Supports command ordering.
  • Supports translation ordering.
  • Supports following write fragmentation operations.
    • Partial write operations
    • 64, 128, 256 byte write operations
  • Supports scrambler/descrambler and can be enabled or disabled.
  • Supports 64B/66B line encoding and decoding.
  • Supports the following error Injection and detection.
    • Scrambler errors
    • Under and oversize frame
    • CRC errors
    • Framing errors
    • Encoding/Decoding errors
    • Training pattern errors
    • Protocol violating errors
  • Supports glitch insertion and detection.
  • Supports monitors, detects and notifies the test bench of significant events such as transactions, warnings, and timing and protocol violations.
  • Supports constraints randomization.
  • Supports status counters for various events on bus.
  • Supports bus accurate timing and timing checks.
  • Supports callbacks in Host, Device and Monitor for user processing of data.
  • OpenCAPI Verification IP comes with complete test suite to test every feature of OpenCAPI specification.
  • Supports functional coverage for complete OpenCAPI features.

Benefits

  • Faster testbench development and more complete verification of OpenCAPI designs.
  • Easy to use command interface simplifies testbench control and configuration of Host and Device.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

OpenCAPI Verification IP Block Diagram

Deliverables

  • Complete regression suite containing all the OpenCAPI testcases.
  • Examples showing how to connect various components, and usage of Host,Device and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

Technical Specifications

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