MIPI_DEBUG_UART Verification IP

Overview

Key Features

• APB common support
• Supports different transfer types including IDLE, WRITE and READ.
• Supports unaligned address accesses.
• Slave memory map support.
• Supports Unmapped address accesses.
• Programmable number of idle cycles
• Ability to inject errors during data transfer.
• Supports FIFO memory.
• Transmit and receive commands allow the user to transmit and receive data.
• Supports character width from 1 bit to 32 bits.
• Configurable receive FIFO depth.
• Supports constraints Randomization.
• Callbacks in transmitter, receiver and monitor for user processing of data.
• On-the-fly protocol and data checking.
• Ability to transmit strings to help verification of SOC.
• Notifies the testbench of significant events such as transactions, warnings, and protocol violations.
• UART Adaptor Verification IP comes with complete testsuite to verify each and every feature of UART Adaptor specification.

Benefits

• Faster testbench development and more complete verification of designs.
• Easy to use command interface simplifies test bench control and configuration of master and slave.
• Simplifies results analysis.
• Integrates easily into Open Vera, System Verilog, and Verilog.
• Runs in every major simulation environment.

Block Diagram

Deliverables

• Complete regression suite containing all the MIPI_DEBUG_UART testcases.
• Examples showing how to connect various components, and usage of BFM and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation contains User's Guide and Release notes.

Technical Specifications