RSA Signature Verification IP Core

Overview

XIP5012C is a very compact Intellectual Property (IP) core designed for RSA (Rivest-Shamir-Adleman) signature verification. XIP5012C supports all modulus lengths up to 4096 bits, and it can also be used for RSA public key exponentiation. RSA signature verification is used in numerous contemporary security protocols and applications, including TLS 1.3.

XIP5012C has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP5012C does not rely on any FPGA manufacturer-specific features.

Key Features

Minimal Resource Requirements: The entire XIP5012C requires less than 280 LUTs (lookup tables) and 2 internal memory blocks (Xilinx® Zynq®-7000). Contact sales@xiphera.com for ASIC resource requirements.
Performance: Despite its small size, XIP5012C can support more than 10 digital signature verification operations per second.
Standard Compliance: XIP5012C is compliant with FIPS 186-4.

Benefits

Fully digital design
Portable to any ASIC or FPGA technology
Fully standard compliant
Easy to integrate
Several bus interfaces available
IP core designed in-house at Xiphera
Technical support by the original designers and cryptographic experts

Block Diagram

Applications

Example use cases of XIP5012C include hardware-isolated verification of digital certificates: XIP5012C verifies the signature of an incoming certificate using a trusted RSA public key (modulus and exponent) from a secure key memory. If and only if XIP5012C successfully verifies the signature, the incoming certificate (and its public key) can be stored in the secure key memory and can be used for verifying other certificates in the future.
In addition to XIP5012C, this use case requires a SHA-256 IP Core (for example XIP3022B or XIP3027C from Xiphera) and a secure key memory; please contact Xiphera for further details.

Deliverables

Please contact sales@xiphera.com for pricing and your preferred delivery method.
XIP5012C can be shipped in a number of formats, including netlist, source code, or encrypted source code.
Additionally, synthesis scripts, a comprehensive testbench, and a detailed datasheet including an integration guide are included..

Technical Specifications

Foundry, Node

Any

Maturity

Hardware Tested

Availability

Immediate

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