MIPI M-PHY HS-G4 IP (M-PHY v4.1) in TSMC 40G

Overview

The MXL-MIPI-M-PHY is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY. The IP can be used as a physical layer for many applications, including interfaces for display, camera, audio, video, memory, power management and Baseband to RFIC. It supports the following standards: CSI-3, DSI-2, Uniport-M (UniPro1.41) LLI and JC-64.1 UFS.
By using efficient Burst mode operation with scalable speeds, significant power savings can be obtained. Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates.

Key Features

  • Supports MIPI® Alliance Specification for M- PHY® Version 4.1.
  • Dual-simplex point-to-point interface with ultra-low voltage differential signaling.
  • Slew-rate control for EMI reduction.
  • Supports HS-MODE; HS-G1, HS-G2, HS-G3, HS-G4.
  • Supports ADAPT sequence for RX equalization in HS-G4.
  • Supports Type-I LS-MODE PWM-G1.
  • 1.248-11.66 Gbps data rate in HS mode.
  • Mixel’s Legorithmic approach allows for large number of different configurations.
  • Burst mode operation for improved power efficiency and low power dissipation.
  • Multiple transmission modes with different bit-signaling and clocking schemes intended for different bandwidth ranges to enable better power efficiency over a huge range of data rates.
  • Multiple power saving modes, where power consumption can be traded-off against recovery time.
  • Symbol coding (8b10b) for spectral conditioning, clock recovery, and in-band control options for both PHY and Protocol Layer.
  • Low power dissipation.
  • Loopback testability support.

Benefits

  • Supports M-PHY HS-G4 and is available in TSMC 40G and other nodes

Block Diagram

MIPI M-PHY HS-G4 IP (M-PHY v4.1) in TSMC 40G Block Diagram

Applications

  • Mobile
  • Displays
  • Cameras/Sensors
  • IoT
  • VR/AR/MR
  • Consumer electronics
  • Automotive
  • Storage

Deliverables

  • Specifications
  • GDSII
  • LVS netlist
  • LEF file
  • IBIS Model
  • Verilog Model
  • Timing Model
  • Integration Guidelines
  • RTL
  • Documentation
  • One year support

Technical Specifications

Foundry, Node
TSMC, 40G
Maturity
Silicon Proven
Availability
Now
TSMC
Silicon Proven: 40nm G
×
Semiconductor IP