MIPI M-PHY IP
The MIPI M-PHY IP is a physical layer interface IP designed for the latest generation of flash memory-based storage and for other high-bandwidth applications that require fast communications channels. The specification, which uses a differential signaling with an embedded clock, is optimized for applications that have a particular need for high data rates, low pin counts, lane scalability and power efficiency. Key applications include connecting flash memory-based storage, cameras and RF subsystems, and for providing chip-to-chip inter-processor communications (IPC).
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MIPI M-PHY IP
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MIPI M-PHY IP
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MIPI M-PHY
- The M-PHY implements MIPI M-PHY protocol V4.1
- The M-PHY protocol specification is a part of a group of communication protocols defined by MIPI® Alliance standards intended for mobile system chip to chip communications
- The M-PHY specification is specifically designed to be suitable for multiple protocols and for a wide range of applications
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Simulation VIP for MIPI M-PHY
- Specification Compliance
- Complies with MIPI M-PHY 4.0, 4.1 and 5.0 specification
- M-PHY Type 1 and Type 2
- Supports Type 1 and Type 2
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MIPI MPHY Verification IP
- Supports 3.0,4.1 and 5.0 MIPI MPHY Specification.
- Support Type-1 and Type-II operations.
- Supports both serial and protocol layer interface.
- Supports all PWM 0-7 gear of operation.
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MIPI MPHY Synthesizable Transactor
- Supports 3.0, 4.0 MIPI MPHY Specification
- Support Type-1 and Type-II operations
- Supports both serial and protocol layer interface
- Supports all PWM 0-7 gear of operation
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MIPI M-PHY Verification IP
- Compliant to MIPI M-PHY Version 5.0
- Supports two SUB-LINKs with configurable number of LANEs in each
- Supports high speed and low speed modes for all modules
- Supports HS-BURST with all HS-GEARs, HS-G1 to HS-G3 in HS-MODE
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MIPI M-PHY Verification IP
- Compliant to MIPI M-PHY Version 5.0
- Supports two SUB-LINKs with configurable number of LANEs in each
- Supports high speed and low speed modes for all modules
- Supports HS-BURST with all HS-GEARs, HS-G1 to HS-G3 in HS-MODE
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MIPI M-PHY Type 1 G5 2TX2RX - TSMC N7 1.8V, North/South Poly Orientation
- Compliant with MIPI M-PHY v5.0 specification
- Supports MIPI UniPro, JEDEC UFS protocols
- Supports High-Speed (HS) Gear1,
- Gear2, Gear3, Gear4 and Gear5 A/B modes
- Supports M-PHY Type-I
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MIPI M-PHY G5 Type 1 2Tx2Rx - TSMC N6 1.8V, North/South Poly Orientation
- Compliant with MIPI M-PHY v5.0 specification
- Supports MIPI UniPro, JEDEC UFS protocols
- Supports High-Speed (HS) Gear1,
- Gear2, Gear3, Gear4 and Gear5 A/B modes
- Supports M-PHY Type-I
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MIPI M-PHY Type 1 G4 2TX2RX - TSMC N5A 1.2V, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 2
- Compliant with MIPI M-PHY v5.0 specification
- Supports MIPI UniPro, JEDEC UFS protocols
- Supports High-Speed (HS) Gear1,
- Gear2, Gear3, Gear4 and Gear5 A/B modes
- Supports M-PHY Type-I
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MIPI MPHY G4 Type 1 1TX1RX - TSMC N5 1.2V, North/South Poly Orientation
- Compliant with MIPI M-PHY v5.0 specification
- Supports MIPI UniPro, JEDEC UFS protocols
- Supports High-Speed (HS) Gear1,
- Gear2, Gear3, Gear4 and Gear5 A/B modes
- Supports M-PHY Type-I