MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 12FFC

Overview

The MIPI M-PHY Gear 4 IP is compliant with the latest MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. A serial interface technology with high bandwidth capabilities and supports HS Gear4 rates up to 11.6Gbps, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. The MIPI M-PHY Gear 4 IP compliant to the RMMI interface which allows UniPro controller and UFS Controller. The MIPI M-PHY provides robust testability by low-cost Build-In-Self-Test (BIST), and receiver eye data monitoring and debugging function for embedded system.

Key Features

  • Compliant with M-PHY Spec 4.1, UniPro Spec 1.8, UFS Spec 3.0
  • Support HS-MODE Gear4(A/B) with data rate up to 11.6Gb/s, and backward compatible
  • Support LS-MODE PWM-G1 to PWM-G5 with data rate up to 144Mb/s
  • Support reference clock frequency with 19.2/26/38.4/52MHz defined in UFS spec.
  • Support RMMI interface for Type-I application
  • Receiver eye open for monitoring and debugging
  • Support Build-In-Self Test(BIST) for low-cost CP/FT
  • Silicon Proven in TSMC 12FFC

Benefits

  • RX:DFE+CTLE, TX:2-tap FFE
  • Max. Channel Loss:~14dB @6GHz Nyquist
  • Low operation current and low standby current
  • Competitive IP PPA leading in the market

Block Diagram

MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 12FFC Block Diagram

Deliverables

  • Application Note / User Manual
  • Behaviour model, and protected RTL codes
  • Protected Post layout netlist and Standard Delay Format (SDF)
  • Library (LIB)
  • Frame view (LEF)
  • Metal GDS (GDSII)
  • Test patterns and Test Documentation

Technical Specifications

Foundry, Node
TSMC 12FFC
Maturity
In Production
Availability
Immediate
TSMC
In Production: 12nm
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Semiconductor IP