MIPI D-PHY IP 4.5Gbps in TSMC N7

Overview

The MXL-DPHY-DSI-TX-T-N07 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5. The PHY can be configured as a MIPI Master supporting display interface DSI/DSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications

Key Features

Supports MIPI Alliance Specification for D-PHY Version 2.5
Consists of 1 Clock lane and 4 Data lanes
Embedded, high performance, and highly programmable PLL
PLL supports SSC mode, Fractional mode, and Integer mode
Supports both low-power mode and high speed mode with integrated SERDES
80 Mbps to 1.5 Gbps data rate per lane without skew calibration in D-PHY mode
4.5 Gbps data rate per lane with skew calibration in high speed D-PHY mode
Supports High Speed TX De-emphasis Equalization
10 Mbps data rate in low-power mode
Low power dissipation
Testability support
Calibrator for resistance termination

Benefits

Area optimized IP that supports MIPI DSI-2 and MIPI CSI-2. Supports v2.5 of the D-PHY specification at 4.5 Gbps/lane and 4 data lanes for an aggregate bandwidth of 18 Gbps.

Block Diagram

Applications

Mobile
Displays
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

TSMC N7, 7nm

Maturity

Available Upon Request

Availability

Now

TSMC

Pre-Silicon: 7nm

Request Info