The MXL-DPHY-CSI-2-RX-T-40LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY.
The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for camera interface applications (CSI2).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
MIPI D-PHY CSI-2 RX (Receiver) in TSMC 40LP
Overview
Key Features
- Consists of 1 Clock lane and 4 Data lanes
- Complies with MIPI Standard 1.1 for D-PHY
- Supports both high speed and low-power modes
- 80 Mbps to 1.5Gbps data rate in high speed mode
- 10 Mbps data rate in low-power mode
- High Speed Deserializers included
- Low power dissipation
Benefits
- Area optimized IP for MIPI D-PHY CSI-2 Receiver silicon proven in 40LP.
Block Diagram
Applications
- Mobile
- Cameras/Sensors
- IoT
- VR/AR/MR
- Consumer electronics
- Automotive
Deliverables
- Specifications
- GDSII
- LVS netlist
- LEF file
- IBIS Model
- Verilog Model
- Timing Model
- Integration Guidelines
- RTL
- Documentation
- One year support
Technical Specifications
Foundry, Node
TSMC 40LP
Maturity
Silicon Proven
Availability
Now
TSMC
Silicon Proven:
40nm
LP
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