The MXL-DPHY-CSI-2-RX is a high- frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY. The IP is configured as a MIPI slave optimized for camera interface applications; CSI-2.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
MIPI D-PHY CSI-2 RX (Receiver) in Samsung 28FDSOI
Overview
Key Features
- Consists of 1 Clock lane and up to 4 Data lanes
- MIPI DPHY V1.1 specifications
- Supports both high speed and low-power modes
- 80 Mbps to 1.5 Gbps data rate in high speed mode
- 10 Mbps data rate in low-power mode
- High Speed Deserializers included
- Low power dissipation
Benefits
- Area optimized IP for MIPI D-PHY CSI-2 Receiver silicon proven in 28FDSOI.
Block Diagram
Applications
- Mobile
- Cameras/Sensors
- IoT
- VR/AR/MR
- Consumer electronics
- Automotive
Deliverables
- Specifications
- GDSII
- LVS netlist
- LEF file
- IBIS Model
- Verilog Model
- Timing Model
- Integration Guidelines
- RTL
- Documentation
- One year support
Technical Specifications
Foundry, Node
Samsung, 28FDSOI
Maturity
Silicon Proven
Availability
Now
Related IPs
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- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI CSI-2 Receiver
- MIPI D-PHY in ON Semiconductor 180nm
- MIPI D-PHY CSI-2 RX (Receiver) in GlobalFoundries 22FDX
- MIPI CSI-2 Receiver v2.0 Controller IP, Compatible with MIPI C-PHY & D-PHY