In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder. The sliding window algorithm is used to reduce the internal memory sizes. Turbo decoder accepts input LLR's with 8-bit precision and outputs the hard decision bits after six full iterations.
LTE Turbo decoder
Overview
Key Features
- 8-bit precision for input LLR
- 13-bit precision for internal calculations
- Provides automatic normalization for internal calculations to avoid hardware overhead
- Supports full 3GPP-LTE and UMTS block size range is supported
- Supports rate 1/3 coded input
- Supports MAX-log-MAP with scaling factor
- 8 parallel-decoding units (with options of 4/2/1 parallel decoding units for smaller block length codes)
- Sliding window algorithm for internal memory reduction
- Uses parallel internal interleaver/de-interleaver
- Payload throughput of up to 43.2 Mbit/s at 6 iterations (111 MHz on Xilinx-XC6VLX760-1FF1760)
- Supports configurable maximum number of iterations and controllable termination for achieving greater throughput
Applications
- 3GPP-LTE.
- UMTS compatible
Deliverables
- System Model (MATLAB / C code).
- Synthesizable Verilog.
- Verilog Test Benches.
- Documentation.
Technical Specifications
Short description
LTE Turbo decoder
Vendor
Vendor Name
Maturity
Mature
Availability
Now
Related IPs
- 4G LTE/LTE-A Turbo Decoder
- 3GPP UMTS LTE 3GPP2 cdma2000 1xEV-DV 1xEV-DO 8 state turbo encoder
- 3GPP UMTS LTE 3GPP2 cdma2000 1xEV-DV 1xEV-DO Turbo Decoder with Optional Viterbi Decoder
- 3GPP LTE 3GPP2 1xEV-DO Turbo Decoder with Ping Pong Input and Output Memories
- LTE / HSPA turbo decoder
- 3GPP LTE Turbo Encoder