LPDDR5 DFI Assertion IP

Overview

Key Features

• Specification Compliance
  • Compliant with DFI version 5.0 Specifications.
  • Supports LPDDR5 devices compliant with JEDEC LPDDR5 SDRAM Standard JESD209-5.pdf, JESD209-5A and LPDDR5X (Draft).
  • Supports for Read data bus inversion.
  • Supports for Write data bus inversion.
  • Supports for DFI disconnect during training.
  • Supports for WCK Control interface.
  • Supports write clock free running mode.
  • Supports data copy low power function and write x operation.
  • Supports for 2:1 and 4:1 CKR mode.
  • Supports all data rates as per specification.
  • Supports write data mask operation.
  • Supports WCK2CK Sync operation.
  • Supports deep sleep mode.
  • Supports power down mode and self-refresh operation.
  • Supports programmable clock frequency of operation.
  • Supports following training modes.
  • Command bus training
  • WCK2CK leveling
  • WCK-DQ training
  • Enhanced RDQS training mode
  • Supports Error signaling.
  • Supports all types of timing and protocol violations detection for timing parameters.
  • Constantly monitors DFI behavior during simulation.
• Assertion IP features
  • Assertion IP includes:
  • System Verilog assertions
  • System Verilog assumptions
  • System Verilog cover properties
  • Synthesizable Verilog Auxiliary code
  • Support Control mode, PHY mode, Monitor mode and Constraint mode.
  • Supports Simulation mode (stimulus from SmartDV DFI LPDDR5 VIP) and Formal mode (stimulus from Formal tool).
  • Rich set of parameters to configure DFI LPDDR5 Assertion IP functionality.

Benefits

• Runs in every major formal and simulation environment.

Block Diagram

Deliverables

• Detailed documentation of Assertion IP usage.
• Documentation also contains User's Guide and Release notes.

Technical Specifications