LPDDR4 DFI Assertion IP

Overview

Key Features

• Specification Compliance
  • Compliant with DFI version 4.0 or 5.0 Specifications.
  • Supports LPDDR4 devices compliant with JEDEC LPDDR4 SDRAM Standard JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C (Proposed), JESD209-4X and LPDDR4Y (Proposed).
  • Supports for Read data-eye training
  • Supports for Read gate training
  • Supports for Write leveling
  • Supports for Write date-eye training
  • Supports for CA training
  • Supports for Read data bus inversion
  • Supports for Write data bus inversion
  • Supports for Combined and multi-configuration channel support
  • Supports for DFI disconnect during training
  • Supports for Write data mask and data strobe features..
  • Supports for ZQ/DQ Calibration commands.
  • Supports for Byte mode.
  • Supports for Single-ended mode.
  • Supports for Power Down features.
  • Supports for Self refresh.
  • Supports for Programmable READ/WRITE Latency timings.
  • Supports for both 16 and 32 Programmable burst lengths.
  • Supports for Burst sequence.
  • Supports Error signaling.
  • Supports Independent Operation & Multi-Configuration Support for LPDDR4.
  • Supports all types of timing and protocol violations detection for timing parameters.
  • Constantly monitors DFI behavior during simulation.
• Assertion IP features
  • Assertion IP includes:
  • System Verilog assertions
  • System Verilog assumptions
  • System Verilog cover properties
  • Synthesizable Verilog Auxiliary code
  • Support Control mode, PHY mode, Monitor mode and Constraint mode.
  • Supports Simulation mode (stimulus from SmartDV DFI LPDDR4 VIP) and Formal mode (stimulus from Formal tool).
  • Rich set of parameters to configure DFI LPDDR4 Assertion IP functionality.

Benefits

• Runs in every major formal and simulation environment.

Block Diagram

Deliverables

• Detailed documentation of Assertion IP usage.
• Documentation also contains User's Guide and Release notes.

Technical Specifications