IP Catalog > Interface IP > Memory Interface IP > LPDDR IP > LPDDR2 IP > LPDDR2 Controller IP > LPDDR2 DFI Assertion IP

LPDDR2 DFI Assertion IP

Overview

DFI LPDDR2 Assertion IP provides an smart way to verify the ARM DFI LPDDR2 component of a SOC or a ASIC. The SmartDV's DFI LPDDR2 Assertion IP is fully compliant with standard DFI LPDDR2 Specification and provides the following features.

LPDDR2 DFI Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR2 DFI Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Specification Compliance
    • Compliant with DFI version 2.1 or higher Specifications.
    • Supports LPDDR2 devices compliant with JEDEC LPDDR2 SDRAM Standard JESD209-2F.pdf and JESD209-2E.pdf.
    • Supports for Read data-eye training.
    • Supports for Read gate training.
    • Supports for Write date-eye training.
    • Supports for DFI disconnect during training.
    • Supports for X8, X16 and X32 modes.
    • Supports for ZQ/DQ calibration.
    • Supports for Overlay window Enable/Disable.
    • Supports for Write data Mask.
    • Supports for Power Down and Deep Power Down features.
    • Supports for Auto Precharge option for each burst access
    • Supports for Programmable burst length: 4, 8, and 16.
    • Supports for the Sequential and Interleave burst types.
    • Supports for input clock stop and frequency change.
    • Supports DRAM Clock disabling feature.
    • Supports Error signaling.
    • Supports Independent Operation & Multi-Configuration Support for LPDDR2.
    • Supports all types of timing and protocol violations detection for timing parameters.
    • Constantly monitors DFI behavior during simulation.
    • Protocol checker fully compliant with DFI 2.1 or higher Specifications.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV DFI LPDDR2 VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure DFI LPDDR2 Assertion IP functionality.

Benefits

  • Runs in every major formal and simulation environment.

Block Diagram

LPDDR2 DFI Assertion IP Block Diagram

Deliverables

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

Request Info

Related IPs

×
Semiconductor IP