Low Power/Ultra Low Power Pseudo 2 Ports SRAM Compiler with Row/Column Redundancy Option, with read assist, write assist, supports process G/LP/LP_eDRAM/ULP/ULPEF
Overview
Memory Compilers
Technical Specifications
Foundry, Node
TSMC 40nm
Maturity
Avaiable
TSMC
Pre-Silicon:
40nm
G
,
40nm
LP
Related IPs
- High Performance/Low Power/Ultra Low Power Pseudo 2 Ports SRAM Compiler with Row/Column Redundancy Option, with read assist, write assist, supports process HP/HPC/HPC+/HPL/HPM/LP/ULP
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- Low Power/Ultra Low Power 2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, with write assist, supports process G/LP/LP_eDRAM/ULP/ULPEF
- Pseudo 2 Ports SRAM Compiler with Row/Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, write assist, supports process FF/P
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