JESD204B Controller

Overview

JESD204B is a JEDEC interfacing standard for high-speed serial communications of digital radio samples and control data between latest generation of data converters (DACs and ADCs) and Digital Signal Processing (DSP) devices implemented generally by FPGA / ASSP / ASICs targets. MTI’s IPC-JESD204B controller solution enables the quickest and most reliable deployment of both the Transmitter (TX) and Receiver (RX) controller modules for flexible and high perfomance data transfers up to 12.5 Gbps (depending on silicon technology target) per lane in compliance with the latest JESD204B.01 2012 standard release. It includes all main features required to support MCDA-ML applications. MTI’s IPC-JESD204B is a self-contained, fully tested and third party interoperable solution widely used today in a number of Tier1 applications for ASIC/ASSP and FPGAs devices.

Key Features

Standard version: JESD204B 2012
Versions Available: Transmitter / Receiver
Applications and Technologies Supported: ASIC, ASSP, FPGA in VHDL-93 RTL
Line rates: 12.5 Gbps
Modes: Modes ML / SL
HD Mode: Supported
Lanes:1 to 8
Converters: 1 to 8
Mapping Interface: 64 bits * NO_CONVERTERS
Sample widths: N = 12, 14, 15 ,16 bits
Data Scrambling: Supported
8b10b coding: Supported
Device Type: MCDA-ML
Configuration and Status: 32bits CPU interface
Mandatory Test Cases: Supported
Deterministic Latency: ClassI
Backward compatibility: Class0

Benefits

High Throughput: Enables up to 12.5 Gbps lane speeds in compliance with JESD204B.01.
High Flexibility: Enables programmable number of converters modules (M) and lanes (L). Supports variable sample width size from 12 to 16 bits at run-time, High Density (HD) mode, multi-lane alignment. Deterministic Latency Class1 support with SYSREF. Backward compatibility with Class 0 devices is also supported.
Multi-application: Supports a wide range of applications including medical imaging, wireless base stations and generic data communications.
Portable :Designed in generic VHDL-93 and targeting any RTL implementation like ASICs, ASSPs and FPGAs.
Deterministic Latency:Enables very accurate knowledge of internal delays required by advanced signal processing techniques based on delay-awareness (MIMO/Beamforming) and in compliance with JESD204B.01 2012 Sub-Class I deterministic latency requirements.

Applications

Supports a wide range of applications including ultrasound, medical imaging, wireless base stations and generic data communications.

Deliverables

User Manual
Vertification Guide
Test Environment for Simulation
Test Cases
IPC Block (encrypted source code or netlist)
FPGA Hardware Test Bed (optional)

Technical Specifications

Foundry, Node

Any

Maturity

Available

Availability