The Mini-LVDS transmitter converts up to 64-bit CMOS data into 16-pairs of Mini-LVDS data stream that can support Single-Link transmission with up to SXGA+ resolution, or Dual-Link transmission with up to UXGA resolution. This IP is suitable for Flat Panel Display applications.
IBM 65nm Mini-LVDS Transmitter
Overview
Key Features
- Process: IBM 65nm 1.0V/2.5V cmos10sf, support metal option (TBD)
- Logic input: total 64-bit data inputs, clock trigger edge selectable
- Mini-LVDS output: Single-Link or Dual-Link; 8-channel data + SP + clock for each link
- Clock freq: input 70M ~ 250MHz, output 140M ~ 500MHz (data mux 4:1)
- Output data rate: max 1Gbps per channel
- VOD and VCM adjustable
- Link skew and channel skew adjustable
- On-chip DLL supports SSC clock of central spread +/-5%, <150kHz
- Individual power-down control for each link
- Individual high-Z control for each output
- Operating junction temperature: -40°C≤TJ≤+125°C
Technical Specifications
Foundry, Node
IBM 65nm