IBM 65nm LVDS Transmitter
Overview
The LVDS transmitter converts 28-bit data into 4-pair LVDS data stream. A phase-locked transmit clock is transmitted in parallel with the data stream over the fifth LVDS channel. Every transmission cycle 28 bits of input data are sampled and transmitted. The transmitter can be programmed for either Rising-edge strobe or Falling-edge strobe through a dedicated pin. The transmitter supports Spread Spectrum Clocking type of signal input and can accurately track Spread Spectrum Clock/Data input.
Key Features
- Supports 20 to 92.8MHz clock
- 28:4 data channel compression ratio at up to 650Mbps per channel data rate
- No special start-up sequence required between clock/data and PD inputs
- Supports Spread Spectrum Clocking, up to 100 kHz frequency modulation & deviations of ±2.5% center spread or -5% down spread
- Clock edge selectable
- No external component required for PLL
- Conforms to the TIA/EIA-644-A LVDS standard
- Supports power down mode. When PD pin is logic high, the output will be tri-state, ensuring low current dissipation in this mode.
- Full industrial operating temperature range: -40 ~ +85℃
- IBM CMOS 10LPE Process (1.2V/2.5V)
Technical Specifications
Short description
IBM 65nm LVDS Transmitter
Vendor
Vendor Name
Foundry, Node
IBM 65nm
Maturity
Silicon Proven