I2C Controller (AMBA APB <-> I2C)
Overview
The I2C Controller provides access to devices with I2C interface. It accepts the Read / Write commands from APB and converts it to the serial I2C access. The controller supports High speed mode with maximum 3.4 Mbps throughput and it is down compatible with fast mode (400kbps) and standard mode (100kbps).
Key Features
- I2C Interface
- Compliant with I2C specification version 2.1
- Supports a simple bi-directional 2-wire bus for efficient inter-IC control
- Supports a Clock generation circuitry to drive I2C clock from APB clock
- Supports 100kbps bit transfer rate in the standard mode, 400kbps in the fast mode and 3.4mbps in the High speed mode.
- APB Interface
- nx8 FIFO to accelerate the data transfer from and to I2C and APB with programmable FIFO watermark.
- Compliant with AMBA-APB (ver-2.0) for integration with SOC implementations
- Supports APB bus speed up to 100 MHz
- Device States are read by periodic polling mechanism or using the interrupt pin.
Deliverables
- I2C-2.1 compliant RTL source code in Verilog for following:
- Master and Slave combined core
- Master only core
- Slave only core
- Synopsys DC synthesis scripts
- Verification Environment with following components:
- Testbench
- APB BFM
- I2C slave Application
- I2C Bus analyser
- Test cases, regression scripts
- User manuals
- Design Docs
Technical Specifications
Foundry, Node
130nm
Maturity
Soft Core
Availability
Now
Related IPs
- APB Fundamental Peripheral IP, I2C controller, Soft IP
- I2C Master Controller w/FIFO (APB Bus)
- I2C Master / Slave Controller w/FIFO (APB Bus)
- I2C Slave Controller with User Register Array / Memory / FIFO / AMBA Interface
- I2C Slave Controller w/FIFO (APB or AHB or AHB-Lite or AXI-Lite Bus)
- I2C Slave Controller - Low Power, Low Noise Config with APB Interface