DFSPI – SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL and QUAD SPI Bus Controller with DDR / DTR support and optional AES Encryption) + … NOR & NAND Flash Memory Support
DCD-SEMI’s latest innovation — a new IP Core offering full compatibility with the functionality of the DFSPI controller, now tailored to support HyperBUS™ memory. Designed with a strong emphasis on ease of integration, this HyperBUS™ controller leverages the industry-standard AXI4 interface, ensuring seamless incorporation into a wide range of modern system architectures.
Its flexible configuration options, accessible via generics, allow developers to fine-tune key operational parameters for specific application needs. Supporting clock speeds of up to 200 MHz, this controller delivers dependable high-speed performance for memory-demanding systems — from embedded applications to more complex SoC environments. With DCD-SEMI’s proven IP quality, this new solution is a reliable choice for developers seeking robust, accessible, and standards-compliant memory control.
HyperBus™ Memory Controller IP Core – Fully Configurable SPI Master/Slave with HyperBus™ and xSPI Support
DCD-SEMI’s advanced HyperBus™ Memory Controller IP Core is a versatile, high-performance solution designed for seamless integration into modern SoCs and FPGA-based systems. Based on our proven DFSPI architecture, this controller bridges easily to APB, AHB, and AXI buses and supports SINGLE, DUAL, QUAD, and OCTAL SPI master/slave modes — making it ideal for a wide range of embedded applications.
This fully configurable SPI controller includes optional support for the HyperBus™ memory protocol and xSPI (Expanded Serial Peripheral Interface – JESD251A), enabling high-speed communication with the latest generation of HyperRAM™ and NOR/NAND Flash memories. The controller also features adjustable serial clock polarity and phase (SCK), ensuring compatibility with a broad array of SPI-based devices.
Key features:
- Support for HyperBus™ and xSPI standards
- Bridges to APB, AHB, and AXI bus interfaces
- Fully programmable SPI clock parameters
- Automatic Slave Select control via SSCR register
- Technology-independent HDL design
- Integrated DMA support (single and multi-transfer modes)
- Customizable configuration to fit any system design
Ideal for designs requiring a HyperBus memory controller IP package, this IP core simplifies communication with popular SPI Flash memories while offering robust support for high-speed, low-pin-count HyperRAM™ devices. Backed by DCD-SEMI’s reliability and customization flexibility, this IP core ensures optimal performance across a wide range of applications.