High Speed Access & Test IP PCIE Version
Overview
High speed access for test and in-chip sensor & monitor data throughout the silicon lifecycle. Within the SiliconMAX Platform, High-Speed Access & Test (HSAT) IP plays a critical role enabling high-speed interfaces such as PCIe, typically already present in SoCs, to be re-used for high-bandwidth production test. Further, this opens up the possibility to reuse the same high speed test packets and to repeat manufacturing tests in-system or in-field, providing visibility of functional or performance degradation during the device’s lifetime. Manufacturing tests can be repeated in-system and/or in-field.
Key Features
- PCIe functional protocol-based high-speed I/O for ATE, in-system & in-field
- Other interfaces (e.g. SPI) for in-system/in-field available
- Configurable Arm® AMBA® AXI slave interface to HSIO
- Configurable scan chains (512 max) and TAP supported
- Full RTL configuration and integration flow or Synopsys TestMAX Manager
- Arm AMBA AXI testbench generation
- Bypass mode allows scan chains to connect to HS Access & Test IP or GPIO pins
- Multiple levels of loop back for link validation
Benefits
- Easily repeat manufacturing tests in-system and in-field
- Reduce test time by eliminating the constraint of GPIO test pin data rate
- Re-use functional HSIO ports (PCIe and USB) for test and other data
- Avoid the need for large numbers of GPIO test pins
- High speed access to PVT & functional monitors and other sensor data
- Bandwidth scales with each new generation of PCIe
Applications
- High speed access to DFT & Silicon monitoring network through entire Silicon Lifecycle
Deliverables
- Datasheet
- Configured RTL file
- Testbench with loop back tests
- Timing constraints
- Cdc constraints
- Synthesis constraint
Technical Specifications
Maturity
Available on Request
Availability
Available