The HBM4 Controller Core is designed for use in applications requiring high memory bandwidth and low latency including AI/ML, HPC, advanced data center workloads and graphics.
The core accepts commands using a simple local interface and translates them to the command sequences required by HBM4 devices. The core also performs all initialization, refresh and power-down functions. The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space.
The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges, further improving overall throughput. The Reorder functionality is fully integrated into the controller command queue increasing throughput and minimizing gate count.
The core supports all HBM4 features, including: data bus inversion (DBI), DQ parity, command / address parity modes, and single-bank refresh and reorder functionality. Add-On Cores such as a Multi-Port Front-End, ECC and AXI can be optionally delivered with the core.
The core is delivered fully integrated and verified with the target HBM4 PHY.
