Globalfoundries 12nm MIPI D-PHY Tx only V1.2@2.5GHz

Overview

Arasan Chip Systems standalone MIPI D-PHY(SM) Transmit only for Globalfoundries 12nm FinFET process nodes.
Arasan's standalone D-PHY Tx only for Global Foundry 12nm IP is compliant with standalone MIPI D-PHY(SM) Tx only v1.2 Spec and is developed on its 2nd generation D-PHY silicon-proven IP to reduce risk while the design is optimized to leverage the GF 12nm technology node for the reduction in area and power compared to our previous designs.
Arasan’s MIPI D-PHY(SM) Tx only for GF 12nm is seamlessly integrated with Arasan's own MIPI Camera Serial Interface (CSI) and MIPI Display Serial interface (DSI) as part of its Total MIPI Imaging and Display IP Solution.
Arasan’s standalone MIPI D-PHY(SM) Tx only for GF 12nm supports speeds of up to 2.5 Gbps for SoC designs.
The Arasan’s GF 12nm MIPI D-PHY Analog Transceiver IP Core is fully compliant with the D-PHY v1.2 specification.
It is a universal PHY that can be configured as a transmitter, receiver, or transceiver.
Arasan’s GF 12nm D-PHY consists of an analog front end to generate and receive the electrical level signals, and a digital back end to control the I/O functions.
Arasan’s GF 12nm D-PHY provides a point-to-point connection between 0host and device that complies with a relevant MIPI® standard. A typical configuration consists of a clock lane and 1-4 data lanes. The host is primarily the source of data, and the device is usually the sink of data. The D-PHY lanes can be configured for unidirectional or bidirectional lane operation, originating at the host, and terminating at the device. It can be configured to operate as a master or as a slave. The D-PHY link supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. In HS mode, the low swing differential signal can support data transfers.
Arasan’s GF 12nm D-PHY Analog Transceiver IP core implements the PPI interface recommended by the MIPI® working groups to easily interface to the required protocols.

Key Features

Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
Supports standard PHY transceiver compliant to MIPI Specification
Supports standard PPI interface compliant to MIPI Specification
Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
Spaced one hot encoding for Low power [LP] data
Supports ultra low power mode, high speed mode and escape mode
Supports one clock lane and up to four data lanes
Data lanes support transfer of data in high speed mode
Clock lane supports unidirectional communication
Supports High speed mode in Forward communication
PHY can be configured as a master or slave
One byte buffer is housed inside the core for both data-out and data-in paths
Activates and disconnects high speed terminators for reception and transmission
Supports error detection mechanism for sequence errors and contentions
Supports contention detection and turn-arounds
Testability for Tx, Rx and PLL
Has clock divider unit to generate clock for parallel data reception and transmission from/to the PPI unit
On-chip clock generation configurable for transmitter only
Process & Foundry
Available in various foundry processes
No external (off-chip) components required
Can be ported to other processes

Benefits

Available in various foundry processes
No external (off-chip) components required
Can be ported to other processes.
Silicon proven
Extensive Quality Methodology

Deliverables

GDS-II Database
LVS Netlist
Physical Abstract Models (LEF)
Timing Models (LIB)
Process Specific Integration Guide

Technical Specifications

Foundry, Node

Globalfoundries 12nm

Maturity

Silicon Proven

Availability

Now

GLOBALFOUNDRIES

Pre-Silicon: 12nm

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